Nowadays, the integration of different function circuit modules into the same semiconductor chip is gradually adopted in the fabrication of an integrated circuit. As known, these function circuit modules have respective operating voltage ranges. It is a challenge of integrating so many function circuit modules having different operating voltage ranges into the same semiconductor chip.
FIG. 1 is a schematic cross-sectional view illustrating a conventional double-diffused-drain high voltage N-type MOSFET (also referred as DDD HV NMOS device). The DDD HV NMOS device is a high voltage semiconductor device produced by the general semiconductor fabricating process. As shown in FIG. 1, the conventional DDD HV NMOS device comprises a substrate 1, a high voltage P-well region (HV P-Well) 10, an N-field region 11 (N-Field), an N-grade region (N-Grade) 12, a heavily N-doped region 13 (N+), and a gate structure 14. As known, the components of the circuit modules with different operating voltage ranges are very distinguished. In addition, a complementary metal-oxide-semiconductor (CMOS) transistor fabricating process is a widely-used semiconductor fabricating process by forming an N-channel metal-oxide-semiconductor field-effect transistor and a P-channel metal-oxide-semiconductor field-effect transistor on the same substrate. In other words, since it is difficult to integrate the steps of this semiconductor fabricating process, the number of photo masks is too huge and the fabricating cost is high. In addition, the device stability of the high voltage metal-oxide-semiconductor is usually unsatisfied. Therefore, there is a need of providing an improved fabricating method for a high voltage semiconductor device so as to obviate the above drawbacks.